[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Better cache replacement policy for CPU caches

 On Saturday, June 15, 2019, 2:49:58 PM PDT, Ryan Carboni <33389 at protonmail.com> wrote:
 On Saturday, June 15, 2019 8:38 AM, jim bell <jdb10987 at yahoo.com> wrote:

>In the mid-1990's I thought of a way that ordinary DRAM could be combined with a set of cached columns, internal to the DRAM chip to implement the caches in the DRAMs themselves.  To simplify a bit, ordinary DRAMs of the mid-1990's era (say, a 4M x 1) might have had 2048 rows by 2048 columns.  A row address is present, RAS falls, and a row of data is read from the storage cells.  The data is put in the column storage, and one bit is read (for read cycles) or written (for write cycles).

>My idea was that instead of having only a single column of storage, the chip would have 4 or 8 or even more of storage.  Access to main memory in a computer tends not to be truly 'random', but is localized:   Program instructions, stack(s), data area(s), etc.    A given column of storage would be relinquished by means of some LRU (least recently used) algorithm.  I think most programs, when running, would statistically limit themselves to 8 data areas  over periods of time of a few thousands of accesses.

>The main reason this should be superior is that the data path between the DRAM array and the cache columns would be internal to the DRAM chip, say, 2048 bits wide (in the example above; probably much wider in modern 4Gbit+ DRAMs. ) 

>I don't know whether they've done anything like this.  
                             Jim Bell

>Great question, I hold deference to your opinions due to your known legal troubles. Perhaps the fact you even dare email me even increases your worthiness.

>I wonder if it is the same reason ECC checking is done in RAM instead of the processor. It seems incredibly unlikely that a sufficient number of altered bits would occur over the lifetime of the chip to result in incorrect data be returned. Afterall, non-ECC is fine (unless you use ZFS), and the probability of receiving a slightly different bit of data over HTTP used to be pretty high at  according to "When The CRC and TCP Checksum Disagree"

>So RAM is not the most likely source of errors, and being able to correct errors at refresh is sort of strange given the cost in die area.

Well, you may remember nearly 40 years ago when Tim May discovered that alpha particles (nuclei of helium atoms) were the big, main source of SEU (single error upsets) in that generation of DRAMS.  This was a huge discovery, although later going to CMOS (from NMOS) technology made alpha-induced soft errors go away.  (Putting the chips in alpha-free plastic would, and did, fix it as well.)
I am very disappointed that the current generation of microprocessor based computers (Ooops!  These days, there's not much else!!!) has gone away from using at least parity bits in DRAM.   How does a computer detect single-bit errors without at least parity bits?   Worse, I think about 2-3 years ago we were discussing "Rowhammer", a tricky programmatic way of 'randomly' changing bits on a given row, by hitting (reading) on the rows to the right and left of it, a number of times.  Do that enough, and that "target" ("victim") row gets upset.  I would think that at least having parity bits would quickly detect such treatment.
At that point, I searched and discovered that Intel was proactively developing a technology in microprocessors to detect "rowhammer", and to more frequently refresh "victim" rows.  "Great!" I think.  I take back have the things I said about Intel.
Full disclosure:  Shortly, I will be trying to sell to Intel my isotope technology to improve the dielectric constant of semiconductor dielectrics.  
                       Jim Bell

-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: text/html
Size: 6349 bytes
Desc: not available
URL: <https://lists.cpunks.org/pipermail/cypherpunks/attachments/20190615/058adfce/attachment.txt>